The present disclosure relates to integrated circuit (IC) chip yield and, more particularly, to a method that improves IC chip yield by providing for pre-test power-optimized bin reassignment following selective voltage binning.
More particularly, total power consumption is a key concern of IC chip designers. Those skilled in the art will recognize that there are two components to total power consumption: dynamic power consumption and leakage power consumption. More specifically, dynamic power consumption refers to the amount of power required to operate an IC chip and is proportional to the value of the supply voltage (Vdd) squared and to the frequency of operation. Leakage power consumption refers to the amount of power consumed by the IC chip when it is inactive and is proportional to the value of the supply voltage (Vdd) and to the leakage current.
Additionally, designers have realized that process parameter variations have a significant impact on IC chip performance (e.g., on operating speed, as indicated by delay). Such process parameter variations are due to variations that occur during manufacturing and include, but are not limited to, variations in channel length, channel width, doping, spacer width, etc. The process window for an IC chip design (also referred to as the process distribution) refers to the performance range for IC manufactured according to the same design and operating using the same voltage supply. This performance range extends from relatively fast IC chips at one end of the process window (i.e., the “fast” end of the process window) to relatively slow IC chips at the opposite end of the process window (i.e., the “slow” end of the process window). An IC chip at the “fast” end of the process window may consume an excessive amount of dynamic power and/or leakage power (i.e., may violate a maximum total power constraint), whereas another IC chip at the “slow” end of the process window may not meet an IC chip performance requirement.
Selective voltage binning is a technique developed in order to reduce power consumption at the “fast” end of the process window, while increasing operating speed at the “slow” end of the process window. Specifically, in selective voltage binning, the process window for an IC chip design is divided into successive intervals and different voltage ranges are assigned to each successive interval such that relatively low voltage ranges are assigned to intervals at the “fast” end of the process window and relatively high voltage ranges are assigned to intervals at the “slow” end of the process window. Subsequently, based on performance measurements (e.g., delay measurements), the IC chips manufactured according to the IC chip design are assigned to different groups, which are referred to as voltage bins and which correspond to the successive intervals, described above. This process of assigning the IC chips to the different groups or, more particularly, to the voltage bins is referred to as selective voltage binning. When such IC chips are shipped for incorporation into products, the voltage ranges associated their respective voltage bins are noted. Operation of relatively fast IC chips at lower voltage ranges minimizes worst-case power consumption and operation of relatively slow IC chips at higher voltage ranges improves their performance (e.g., increases their operating speed/reduces their delay).
One drawback to selective voltage binning, however, is that, once IC chips are assigned to the different voltage bins, as described above, they are tested and that testing is performed at a bin-specific minimum test voltage. The bin-specific minimum test voltage can, for example, be equal to the minimum voltage (Vmin) of the voltage range assigned to the voltage bin. Alternatively, in order to guarantee proper timing even during worst-case voltage drop events, the bin-specific minimum test voltage can be equal to the minimum voltage (Vmin) of the voltage range assigned to the voltage bin less some predetermined margin (also referred to herein as a guardband voltage). However, because, at low voltages, some IC chips exhibit relatively high sensitivity to process parameter variations that can lead to performance fails, testing of integrated circuit chips at such bin-specific minimum test voltages can have a significant impact on IC chip yield.